1. Field of the Invention
The present invention relates to a driver circuit unit, and more particularly to a driver circuit unit for issuing data to a transmission line.
2. Description of the Related Art
A so-called driver circuit unit functions to issue transmitted data having been received therein to a receiver through a transmission line. Inputted to the above driver circuit unit as input signals are: positive-phase data which is the above mentioned transmitted data having been received in the driver circuit unit; and, negative-phase data which is one reversed in phase of the positive-phase data. Further, issued from the above driver circuit unit to the receiver are: an output signal corresponding to the above positive-phase data; and, an negative-phase output signal corresponding to the above one reversed in phase of the positive-phase data. More specifically, as shown in FIG. 4, inputted to a conventional driver circuit 101 are: positive-phase data 201 which is the above-mentioned transmitted data and a negative-phase data 202.
For example, as shown in FIG. 5, when the positive-phase data 201 is constructed of a series of signals with logic levels H and L, i.e., a series of signals with high level (H), high level (H), low level (L), high level (H), low level (L) and low level (L) sequentially arranged in a row in the above-mentioned order, the negative-phase data 202 is constructed of a series of the negative-phase ones of the signals with the above-mentioned logic levels. In other words, the negative-phase data 202 is constructed of a series of low level (L), low level (L), high level (H), low level (L), high level (H) and high level (H) sequentially arranged in a row in the above-mentioned order, as shown in FIG. 5.
In operation, as shown in FIG. 4, when the conventional driver circuit 101 receives the positive-phase data 201 together with the negative-phase data 202, a pair of switches 101A, 101B perform their switching operations in accordance with these two data 201, 202. In other words, in the driver circuit 101, when the positive-phase data 201 is in the high level, a resistor 101c is connected with a power supply line(+). In contrast with this, when the positive-phase data 201 is in the low level, the resistor 101C is connected to the ground. Further, in the driver circuit 101, when the negative-phase data 202 is in the low level, a resistor 101D is connected to the ground. In contrast with this, when the negative-phase data 202 is in the high level, the resistor 101D is connected with the power supply line.
As a result, when the above-mentioned transmitted data is in the high level, the resistor 101C has a voltage equal to that V.sub.DD of the power supply line, and the resistor 101D is held at the ground level in voltage. On the other hand, when the transmitted data is in the low level, the resistor 101C is connected to the ground, and the resistor 101D is held at the voltage VDD of the power supply line.
The resistors 101C and 101D of the driver circuit 101 are connected with coaxial cables forming transmission lines 102 and 103, respectively. At this time, in the driver circuit 101, the positive-phase data 201 and the negative-phase data 202 are transmitted from the driver circuit 101 to the transmission lines 102 and 103, respectively, provided that the resistors 101C, 101D are used to have the impedance of the driver circuit 101 matched to that of each of the transmission lines 102 and 103.
In a receiver 104 shown in FIG. 4, a signal produced between a pair of the transmission lines 102 and 103 is received in a series circuit of a pair of resistors 104A, 104B. A node N interposed between the resistors 104A, 104B is connected to the ground through a capacitor 104C. In operation, in the receiver 104, when the above-mentioned transmitted data is in the high level, an electric current flows in the direction of the arrow 104E through the series circuit of the resistors 104A, 104B. On the other hand, when the transmitted data is in the low level, the electric current flows in the direction of the arrow 104F through the above series circuit of the resistors 104A, 104B. As a result, an input signal 211 is produced at a node "P" located between the resistor 104A and the transmission line 102. On the other hand, another input signal 212 is produced at a node "Q" located between the resistor 104B and the transmission line 103. The thus produced input signals 211, 212 are inputted to a differential operation portion 104D.
In this differential operation portion 104D, the electric current flowing in the direction of the arrow 104E produces a high level signal which is issued from the differential operation portion 104D. Also in this differential operation portion 104D, the electric current flowing in the direction of the arrow 104F produces a low level signal which is also issued from the differential operation portion 104D.
This differential operation portion 104D is shown in FIG. 6. The differential operation portion 104D shown in FIG. 6 is constructed of a two-stage circuit which is provided with both a differential amplifier 110 and an inverter 120. As shown in FIG. 6, the differential amplifier 110 is constructed of: a plurality of P (i.e., Positive) type MOS (i.e., Metal Oxide Semiconductor) transistors 111, 112, 113; and, a pair of N (i.e., Negative) type MOS transistors 114, 115. On the other hand, the inverter 120 is constructed of a P type MOS transistor 121 and an N type MOS transistor 122.
Both the MOS transistors 112, 113 of the differential amplifier 110 operate upon receipt of a constant electric current supplied from the MOS transistor 111. Inputted to the MOS transistor 112 through an input terminal 131 is an input signal 211 generated at the node "P" shown in FIG. 4. On the other hand, inputted to the other MOS transistor 113 through an input terminal 132 is an input signal 212 generated at the node "Q" shown in FIG. 4.
In operation, when the input signal 211 inputted to the input terminal 131 is higher in level than the input signal inputted to the input terminal 132 (in other words, when the transmitted data mentioned above is in the high level), the MOS transistor 112 is turned OFF so as to be non-conductive, while the other MOS transistor 113 is turned ON so as to be conductive. Due to this, the constant electric current issued from the MOS transistor 111 is supplied, through the MOS transistor 113, to the MOS transistor 115 which serves as a resistor, so that a node "R", through which a drain of the MOS transistor 113 is connected with a drain of the MOS transistor 115, becomes the high level. When this node "R" becomes the high level, the MOS transistor 114 is turned ON so as to be conductive, so that a node "S" through which a drain of the MOS transistor 114 is connected with a drain of the MOS transistor 112 becomes the low level.
When the node "S" becomes the low level, the MOS transistor 121 is turned ON so as to be conductive, while the MOS transistor 122 is turned OFF so as to be non-conductive. As a result, an output terminal 133, which forms a node trough which a drain of the MOS transistor 121 is connected with a drain of the MOS transistor 122, becomes the high level.
In contrast with this, when the input signal 211 inputted to the input terminal 131 is lower in level than the other input signal 212 inputted to the input terminal 132 (in other words, when the transmitted data described in the above is in the low level), the MOS transistor 112 is turned ON so as to be conductive, while the other MOS transistor 113 is turned OFF so as to be non-conductive . Since the MOS transistor 112 is turned ON so as to be conductive while the other MOS transistor 113 is turned OFF so as to be non-conductive as described above, the node "R" becomes the low level so that the MOS transistor 114 is turned OFF so as to be non-conductive, whereby the other node "S" becomes the high level.
When the node "S" becomes the high level, the MOS transistor 121 is turned OFF so as to be non-conductive and the other MOS transistor 122 is turned ON so as to be conductive. As a result, the output terminal 133 becomes the low level.
As described above, the differential operation portion 104D reproduces the above-described transmitted data of the driver circuit 101 to issue it therefrom. Problems to be solved by the present invention are inherent in the related art as follows: namely, the input signals 211 and 212, both of which are inputted to the differential operation portion 104D of the receiver 104 shown in FIG. 4, are voltages developed at the nodes p and Q, respectively. Consequently, when the logic levels representing the high and the low level of these input signals 211, 212 vary, the following problems occur.
For example, when the logic levels of the input signals 211, 212 are low, a voltage developed across the gate-source of each of the MOS transistors 112, 113 shown in FIG. 6 becomes large, which makes it possible for each of the MOS transistors 112, 113 to operate in a linear region. Consequently, in contrast with the ON and OFF operations in its saturation region, each of MOS transistors 112, 113 produces at a node "S" a signal with a level corresponding to the logic level of the input signal 211. In other words, produced at the node "S" in the above is a signal with a level intermediate between the high and the low signal levels produced in ordinary ON/OFF operations. Due to this, a malfunction often occurs in the inverter 120 in its inversion operation, which makes it substantially impossible for the receiver 104 to issue a signal corresponding to the above-mentioned transmitted data of the driver circuit 101.
On the other hand, when the logic level of the input signal 211 is high, the source voltage of each of the MOS transistors 112, 113 becomes high. As a result, a voltage developed across the drain-source of the MOS transistor 111 shown in FIG. 6 becomes small, which makes it possible for the MOS transistor 111 to operate in a linear region. Consequently, an electric current passing through the MOS transistor 111 is reduced. Due to this, for example, the MOS transistor 113 is turned ON so as to be conductive, which causes the MOS transistor 114 to malfunction in its ON/OFF operations since a voltage developed at the node "R" is reduced due to reduction in current supplied from the MOS transistor 111, even though such voltage at the node "R" should be kept at a high level.